In a communication circuit for transmitting a digital signal, a clock signal to be a reference of timing to synchronize internal circuits and communication circuits is used and a circuit for generating a clock signal of a frequency according to a transmission rate is required. Recently, a serial transmission system suitable for the enhancement of a transmission rate is often used. And many serializer/deserializer (SERDES) circuits that convert parallel signals to high speed serial signals for transmitting the signals using time division multiplexing method are used.
An example in which a ring oscillator is used for a phase locked loop (PLL) that generates a clock signal in a microprocessor and a digital signal communication circuit is disclosed in JP-A-1999-298302 and JP-A-2001-358565. For a countermeasure for the frequency variation of PLL, methods to suppress frequency variation due to ambient temperature, process variation and supply voltage are disclosed in JP-A-2003-283305, JP-A-2005-333484; JP-A-2002-290212, JP-A-2005-130092 and JP-A-2003-132676.